As Moore's law approaches its demise and the cost per transistor increases below the 22 nm node, device makers are pushed to seek alternative solutions to achieve higher yield, shorter interconnect length, lower delays, lower power, smaller footprint, reduced weight and higher performance. In a homogeneous 2.5D/3D integration approach, a single chip is partitioned into a number of smaller chips. The smaller chips are then assembled on an interposer and wired together to form a functional chip. In a heterogeneous 2.5D/3D integration approach, a single chip consists of a number of circuitry blocks such as memory, logic, DSP, and RF, each separated into a smaller chip. The smaller chips can be manufactured by different foundries and can be of different process nodes. The smaller chips are then assembled on an interposer and wired together to form a functional chip.
The semiconductor industry has been transitioning from a 2D monolithic approach to a 2.5D/3D heterogeneous approach at a much slower rate than expected, mainly due to high costs. The high costs arise from manufacturing, poor reliability, and low yield. Establishing a supply chain for a 2.5D/3D device depends on the device market and volume. However, costs, reliability, and yield are the fronts that are hitting the industry the most.
A silicon interposer is the building block and an enabler for 2.5D/3D integration, whether homogeneous or heterogeneous. In a conventional silicon interposer manufacturing flow, blind vias with a diameter of 10 um are created within the wafer followed by back-grinding the wafer to 100 um nominal in order to reveal the vias from the backside, creating what is known as through-silicon vias (TSV). Such an interposer is known as an interposer with 10:100 aspect ratio, implying 10 um via diameter and 100 um interposer thickness. This process is called “wafer thining and via reveal process.” In reality, not all of the blind vias are etched with equal depth, as there is always considerable variation in blind via depth due to process variation. With more than 2 um variation in blind via depth, considerable contamination occurs during the back-grind process in order to reveal all of the blind vias. In general, thinning and the via reveal process has proven to have a tremendously negative impact on the yield and has given the 2.5D/3D integration a reputation as a costly process that is justified only if the market demands the technology and can absorb the associated cost.
As mentioned above, in a conventional 2.5D/3D integration and assembly, a single chip is partitioned into multiple other chips or so-called partitions, whether homogeneous or heterogeneous. Partitions are then bumped using copper pillar bumping technology. Copper pillar is used for fine pitch bumping, normally when the bump pitch is less than 80 micron. A typical partition can have a bump pitch of 45 microns or smaller. Partitions are assembled on a thin silicon interposer with typical aspect ratio of 10:100. The back side of the interposer has a typical bump pitch of 150 micron or more in order to resemble the industry standard flip chip bump pitch in practice as of today and is bumped using solder bump material. The Silicon interposer is then assembled on a multi-layer organic build up substrate. A ball grid array (BGA) with a typical pitch of 1 mm is attached to the back side of the organic substrate. The organic substrate is then assembled on a printed circuit board (PCB).
The conventional silicon interposer TSV manufacturing process with sequential bumping and assemblies has resulted in a costly platform which has inhibited the launch of 2.5D/3D products in many market sectors.
According to industry sources, 40% of the cost associated with manufacturing a silicon interposer is attributed to wafer thinning and the back-grinding via reveal process. A recent independent study sheds light on the cost break down of processing steps required for manufacturing a conventional 31×31 mm2, 100 um thin silicon interposer with 12 um TSV diameter, 3 copper damascene RDL layers with 65 nm design rule for routing on the top layer. According to the study, 19% of the cost contribution is attributed to the wafer thinning and TSV reveal process, 20% to wafer bonding/debonding process, 19% to TSV filling process, 18% to RDL process, 13% to via etching process and only 5% to the bumping process.
The processes related to TSVs include the wafer thinning and TSV reveal process, the wafer bonding and debonding process, and the TSV copper via fill process. These three processes contribute to almost 60% of the overall cost of manufacturing.
Interposers in practice today consist of redistribution layers (RDL), RDL vias, and through substrate/silicon vias (TSVs). FIG. 0A is a side view of an assembly employing through substrate vias according to prior art. TSVs 10 are used to transition signals 20 and supplies from the top 35 of the substrate 30 to the bottom 40 and vice versa through the substrate core thickness. TSVs are constrained by diameter, height, and pitch. Thus, a limited number of TSVs can be placed in a substrate, moreover, it has a negative impact on signal and power integrity.